System Verilog for Verification | A guide to learning the Testbench Language Features
About this Book
System Verilog is a new language that lets you build testbenches using Object-Oriented Programming (OOP) The book includes many exam ples on how to build a basic coverage-driven, constrained-random layered testbench.
If you have only written tests using Verilog or VHDL, this book shows you how to move up to the new language features Vera and Specman.
Who should read this book?
This book shows you how to move up to the new language features Vera and Specman users can learn how one language can be used for both design and verification. I spen much of my career ing procedural languages such as C and Verilog to write tests, and had to releamm everything when OOP verification languages came along. I wrote this book so that you won't have to repeat them.
SystemVerilog for Verification has many improvements over the first edition that was published in 2006. There are over 50 new pages in the original ten chapters, and over 70 new examples. This edition is almost 1/3 larger than the original. All mistakes are mine, from poor grammar to code that was obviously written on the morning after a 18-hour flight from Asia to Boston.
SystemVerilog, a new language for describing hardware for simulation and synthesis. The first two versions of Verilog had only simple constructs for creating tests. As design sizes outgrew the veri fication capabilities of the language. Companies that did not want to pay for hundreds of man-years creating their own custom tools. Accellera's goal was met in November 2005.
Importance of a unified language
SystemVerilog unifies syntax and semantics of design and verification tools. Design engineer may not be able to write an object-oriented testbench environment, but it is fairly straightforward to read such a test and understand what is happening. The value of an HVL is its ability to create high level, flexible tests, not its loop constructs or declaration style. Systemverilog is based on Verilog constructs that engineers have used for decades.
SystemVerilog allows the user to construct reliable, repeatable verification environments, in a consistent syntax, that can be used across multiple projects. This book focuses on techniques for verification using constrained-ran dom tests that use functional coverage to measure progress and direct the verification. SystemC can also be used for architectural modeling. The IEEE standard mentions archi tectural modeling before design, assertions, and test.
SystemVerilog Language Reference Manual contains hundreds of new features. All of the examples have been verified with Synopsys' Chronologic VCS and 2008.03. If you think you have found a mistake, please check my web site for the Errata page. I will send you a free, autographed book if you are the first to find a mistake in a chapter.
SystemVerilog is a new book that lets you test your knowledge of the system and its features. Author: I want to thank all the peo ple who spent countless hours helping me leam System Verilog and reviewing the book that you now hold in your hand A big thanks to Shalom Bresticker. Janick Bergeron provided inspiration, top-quality reviews, and top-level guidance.
The DPI allows you to call C routines as if they are just another System Verilog rou tine, passing SystemVerilog types directly into C. This has less overhead than the PLI. which builds argument lists, and always has to keep track of the calling context, not to mention the complexity of having up to four C routines for every system task.
Additionally, with the DPI, your C code can call System Verilog routines, allowing external applications to control simulation. With the PLI you would need trigger vari ables and more argument lists, and you have to worry about subtle bugs from multiple calls to time-consuming tasks.
The most difficult part of the DPI is mapping System Verilog types to C, especially if you have structures and classes that are shared between the two languages. If you can master this problem, you can connect almost any application to SystemVerilog.